Synplify

Synplify is a Verilog and VHDL synthesis tool for FPGAs/CPLDs that targets Actel, Altera, Cypress, Lucent Technologies (formerly AT&T Microelectronics), QuickLogic and Xilinx devices. It converts your HDL designs into high-performance, low-area device netlists using special device-specific optimization, mapping, and module generation techniques developed by Synplicity. Synplify also includes an integrated language-sensitive editor that highlights syntax and synthesis errors for fast design development.

Synplify Support:

Vendor       Architectures        Output Format  File Extension

Actel        Act2/1200XL, Act3,     EDIF             .edn
             3200DX       
Altera       MAX5000, 7000, 9000;   EDIF             .edf
             FLEX8000, FLEX10000
Lucent       ORCA 1C, 2C            EDIF             .edn
Cypress      pASIC380               QDIF             .qdf
QuickLogic   pASIC                  QDIF             .qdf
Xilinx       XC3000, XC4000, XC5000 XNF              .xnf

More Info:

Datasheet (benefits and features)
Picture of User Interface
Run Time Comparison Graph

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